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The Cortex-M0 / M0+ / M1 include a minor subset of Thumb-2 instructions (BL, DMB, DSB, ISB, MRS, MSR).

The Cortex-M0 / M0+ / M1 include Thumb-1 instructions, except new instructions (CBZ, CBNZ, IT) which were added in ARMv7-M architecture.

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Note: Limited public information is available for the Cortex-M35P until its Technical Reference Manual is released in 2019.

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Note: Software should validate the existence of a feature before attempting to use it.

The bit-band option can be added to the M0/M0+ using the Cortex-M System Design Kit.

Note: Most Cortex-M3 and M4 chips have bit-band and MPU.

Other than cache, it is typically the fastest RAM in the microcontroller.ĪRM Cortex-M optional components ARM Core

Tightly-Coupled Memory (TCM): Low-latency RAM that is used to hold critical routines, data, stacks.

It supports up to eight different regions, each of which can be split into a further eight equal-size sub-regions.

Memory Protection Unit (MPU): Provides support for protecting regions of memory through enforcing privilege and access rules.

Some Cortex-M0 and Cortex-M0+ microcontrollers have bit-band. Though the bit-band is optional, it is less common to find a Cortex-M3 and Cortex-M4 microcontroller without it. In particular, individual bits can be set, cleared, or toggled from C/C++ without performing a read-modify-write sequence of instructions. This allows every individual bit in the bit-band region to be directly accessible from a word-aligned address. For example, writing to an alias word will set or clear the corresponding bit in the bit-band region.

Bit-Band: Maps a complete word of memory onto a single bit in the bit-band region.

If a Cortex-M33 microcontroller has the Security Extension option, then it has two SysTicks, one Secure and one Non-secure. Though the SysTick timer is optional, it is very rare to find a Cortex-M microcontroller without it. When present, it also provides an additional configurable priority SysTick interrupt.

SysTick timer: A 24-bit system timer that extends the functionality of both the processor and the Nested Vectored Interrupt Controller (NVIC).

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